1. Field of the Invention
This invention relates to a semiconductor integrated circuit formed on a chip and having a substrate-bias circuit, and more particularly to a substrate bias generation circuit used in a CMOS DRAM (complementary metal oxide semiconductor dynamic random access memory) of relatively large capacity.
2. Description of the Related Art
In a semiconductor memory using N-channel MOS FETs, for example, the semiconductor substrate is injected holes by impact ionization or the like. FIG. 1A is a cross sectional view of a CMOS inverter and FIG. 1B is a circuit diagram of the CMOS inverter. In FIG. 1A, element 32 denotes n-type semiconductor well area and element 10 denotes p-type semiconductor substrate. As shown in FIGS. 1A and 1B, impact ionization is a phenomenon in which holes 30 are generated by current I which flows in a channel created by a high level voltage applied to the gate of the N-channel MOS FET.
Therefore, as the memory capacity increases and the current in the memory increases, more holes are increasingly injected into the semiconductor substrate. When the holes are injected into the semiconductor substrate, and potential of the substrate is locally rised, junction between n.sup.+ area applied Vss level voltage and p-type substrate is forward biased. Therefore, electrons are injected from n.sup.+ area into the p-type substrate. The electrons may reach memory cells, and destroy the data in the memory cells, or deteriorate the data retaining characteristic.
Therefore, a substrate bias generation circuit 11 for negatively biasing the substrate is provided for a memory of relatively large capacity, in order to absorb the holes generated by the impact ionization. That is, a substrate bias voltage Vsub (for example, -2.5 to -3 V) is derived from a power source voltage Vcc (for example, +5 V) applied from the exterior to the chip and an output voltage thereof is applied to the semiconductor substrate. The bias circuit includes a ring oscillator, a capacitor C and diodes D1 and D2 as shown in FIG. 2, for example. The holes 30 are attracted by the bias circuit 11 and flow in a resistor R of the substrate as a substrate current i.
In particular when the substrate bias generation circuit is used in a dynamic RAM, it functions to prevent the PN junction of an input section being turned on by the undershoot of an input signal and causing a large amount of electrons to be injected into the substrate, destroying data stored in the memory cell.
However, recently, as the memory capacity and the operation speed of a RAM such as a 4M-bit dynamic RAM are increased, it is required for MOS transistors used in the RAM to drive larger capacitance at a higher operation speed. As a result, the current driving ability of the individual transistor is increased. For example, in the dynamic RAM, a data line restore circuit or data output buffer generates a large current. As a result, a large current flows in the semiconductor integrated circuit chip and the amount of carriers, which are generated by the impact ionization and injected into the semiconductor substrate are increased. In addition, since the chip area is increased, the resistance and capacitance of the semiconductor substrate are also increased.
In FIG. 3, Ih denotes a current caused by holes injected into the semiconductor substrate by impact ionization or the like, R denotes the resistance of the substrate, 31 denotes the substrate bias generation circuit, C0 denotes a capacitor near the substrate bias generation circuit, C1 denotes a capacitor of a circuit positioned at the remotest position from the substrate bias generation circuit, i denotes a substrate current flowing in the substrate, and ibb denotes an absorption current of the bias circuit. As is clearly understood from FIG. 3, since the resistance of the resistor R and the capacitances of the capacitors C0 and C1 are increased as the capacity of the semiconductor integrated circuit is increased, the time constant of the current i becomes larger. Therefore, when a group of circuits lying in an area far from the substrate bias generation circuit 31 on the chip are operated, a time delay caused by the presence of the capacitors C0 and C1 and the resistor R of the semiconductor substrate may occur in a period from when carriers (for example, holes) are injected into the semiconductor substrate until the carriers are absorbed into the substrate bias generation circuit via the resistor R of the semiconductor substrate.
The time delay causes the substrate potential at the remotest area from the substrate bias generation circuit to be set to a potential which temporarily deviates from the potential determined by the substrate bias generation circuit. As a result, the back-gate bias of a MOS transistor lying at the remotest position from the substrate bias generation circuit is temporarily changed. Accordingly, the gate threshold voltage of the MOS transistor is varied. As a result, the noise margin of the circuit is lowered, causing an erroneous operation. Further, the MOS transistor which is formed as an enhancement type is changed into a depletion type, setting the circuit into an inoperative condition.